1. Field of the Invention
The present invention relates in general to device isolation techniques. More particularly, it relates to an method of making an isolation trench structure in a semiconductor substrate.
2. Description of the Related Arts
As integrated circuit devices become more highly integrated and include finer geometries, it can become increasingly important to reduce the size of isolation regions that are used to isolate active devices such as transistors from one another. The initial formation of isolation regions may determine the size of an active region and the process margins for subsequent processing. Accordingly, reduction of the size of the isolation regions is desirable.
LOCal Oxidation of Silicon (LOCOS) is widely used for fabricating isolation regions in integrated circuits. The LOCOS process can be simple. However, in highly integrated devices, such as 256 MB DRAM devices, as the width of the isolation region is reduced, a punchthrough may be caused by xe2x80x9cbird""s beakxe2x80x9d during oxidation. This may reduce the thickness of a field oxide film and may reduce the size of the active regions. An isolation method may also use a trench, rather than forming a field oxide layer by thermal oxidation. In trench isolation methods, a trench is formed on the integrated circuit device and is filled with an insulating material such as an oxide layer, to thereby form an isolation region that can be smaller than that formed by the LOCOS method. Moreover, problems of the LOCOS method and problems caused by the thermal oxidation can be controlled.
A trench isolation method is disclosed in xe2x80x9cA Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMsxe2x80x9d, IEDM Tech. Digest, pp. 57-60, 1993, by P. Fazan et al. As disclosed, a pad oxide layer and a silicon nitride layer are formed and patterned on an integrated circuit substrate. The integrated circuit substrate is then etched using the patterned silicon nitride layer and pad oxide layer as a mask, to form a trench. Then, a sidewall of the trench is thermally oxidized, and an oxide layer is formed in the trench by chemical vapor deposition. The oxide layer is then planarized by Chemical Mechanical Polishing (CMP). Subsequently, the silicon nitride layer is removed, and an oxide spacer is formed on the sidewall of the oxide layer. The pad oxide layer is then wet etched to complete an isolation layer and to form a gate oxide layer and a gate.
The ever-present pressure upon the microelectronics industry to shrink electronic devices and to crowd a higher number of electronic devices onto a single die, called miniaturization, has required the use of such structures as isolation trenches. However, according to conventional trench isolation methods, reduction of the width of the isolation regions is limited by lithography resolution. In consequence, it would be a significant improvement in the state of the art if the width of the isolation region can be reduced beyond lithography limit.
An object of the invention is to provide a method of making isolation trenches having the widths beyond lithography limit.
To attain the above and other objects, the present invention provides a method of making an isolation trench structure in a semiconductor substrate. A first layer is formed on a semiconductor substrate. By way of non-limiting example, the first layer is a dielectric layer such as an oxide layer. The dielectric layer is subsequently patterned to form insulator islands to protect active areas in the semiconductor substrate. A second layer is conformally formed over the dielectric islands and the remaining portions of the substrate. The second layer is then anisotropically etched to form spacers on sidewalls of the insulator islands. The substrate is subjected to a thermal oxidation process, thereby forming thermal oxide masks at positions which are not covered with the insulator islands and the sidewall spacers. Thereafter, the sidewall spacers are selectively removed to expose the substrate between the islands and the thermal oxide masks. Then, isolation trenches are etched through the exposed substrate using the islands and the thermal oxide masks as masks.
According to the invention, because the width of the trench is determined by the width of the sacrificial spacer, not by lithography resolution, the isolation trench can be made narrower beyond lithography limit.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description which makes reference to the accompanying drawings.